As the demand to push semiconductor device features deeper into the sub-micron range has increased, numerous techniques have been developed for extending the ability of photolithograpic processes to define increasingly smaller image sizes. Since the 1970's the resolution limits of optical lithography have been reduced from about 1.5 microns down to about 0.2 microns and lower. Advancements, such as shorter exposure wavelengths, variable numerical aperture exposure lenses and phase shift masks, have contributed greatly to the progress that has occurred. In concert, anti-reflective coatings (ARC) have increasingly been incorporated into semiconductor process sequences, as a means of further enhancing critical dimension (CD) control during sub-micron photolithography steps. The use of such anti-reflective coatings can be a very effective means of minimizing photoresist exposure problems that would, otherwise, be aggravated by the high reflectivity of underlying wafer surfaces. During a photoresist exposure operation, photons that are reflected back up into the resist layer, at angles other than 90 degrees, can lead to distorted images. Scattered photons from rough underlying surfaces can lead to a general reduction in image contrast. Furthermore, scattered photons from underlying steps can lead to notched images. Even for the more ideal case of 90 degree reflection from a smooth flat underlying surface, the resultant standing wave pattern in the resist layer can also lead to a reduction in image contrast. These image control problems can occur when photoresist layers are exposed over reflective surfaces such as aluminum and polysilicon, for example. These problems can be greatly minimized by first depositing an anti-reflective coating, (ARC) prior to the application of the photoresist layer. The ARC may be in the form of a highly absorbing layer, such as a polymer, or a thin layer of titanium (Ti) or silicon oxynitride (SiON), for example. Ideally, to help minimize reflectivity, the optical properties of ARCs should be optically optimized with any underlying layers, the overlying photoresist layer and the wavelength of the exposure source. Consequently, S.sub.i ON layers, by virtue of having process controllable optical properties, have become particularly attractive as ARCs.
When S.sub.i ON is deposited by CVD, for example, its optical properties can be adjusted by changing the atomic composition of the film.
There are numerous methodologies used for employing ARCs. ARCs have been used in the form of localized as well as blanket layers which may or may not be deliberatly removed during subsequent processing. In the case of the present invention, a method is taught for the removal of a blanket SiON layer after it has been used as an ARC for improving the image control of sub-micron polysilicon gates. Although quite advantageous from the standpoint of having adjustable optical properties, SiON as an ARC, however, is not totally devoid of its own problems, as addressed in the following patent by Tsukamoto, et. al.
U.S. Pat. No. 5,600,165 to Tsukamoto, et. al., teaches a method for using SiON as an ARC while also avoiding a device degradation problem associated With the hydrogen that is contained within the SiON film. When SiON is used as an ARC to improve the image definition of a sub-micron polysilicon gate, for example, and then allowed to remain during subsequent hot processing, hydrogen in the SiON film can diffuse down through the underlying polysilicon and gate oxide. Once the hydrogen reaches the gate oxide, its resistance to hot carrier damage can be reduced and this can, in turn, lead to unacceptable device threshold voltage instability. The patent of Tsukamoto et.al., teaches several methods to solve this potential hydrogen related problem, by means of creating hydrogen diffusion barriers (such as thin layers of silicon nitride of titanium silicide) between the SiON ARC and the gate oxide region of active devices. However, since the inventors deliberately left the SiON layer on after it was used as an ARC, no method was taught for how to remove it.
There have been prior publications that do discuss methods for the removal of SiON layers. U.S. Pat. No. 5,741,396, to Loewenstein, teaches dry isotropic etching methods for the removal of nitride, oxynitride and polysilicon layers, while not removing thin pad oxide layers that are used to protect underlying silicon regions from being attacked at the same time. The invention also discusses the use of hot phosphoric acid (H.sub.3 PO.sub.4), as a wet etching means of removing nitride and oxynitride films, in conjunction with thin pad oxides to protect underlying silicon regions. However, a method for the formation and wet etch removal of a S.sub.i ON film and thin pad oxide combination that have been optimized as an ARC for the photolithographic definition of polysilicon gates is not addressed.
U.S. Pat. No. 5,269,879, to Rhoades, et. al., also teaches methodologies for the dry etching of insulating films, such as silicon dioxide, silicon nitride and silicon oxynitride. This invention addresses the formation of via holes down to the underlying conductive regions of devices, while avoiding the problem of damaging the conductive regions, such as aluminum or titanium silicide, for example. The etching means includes a fluoride-containing gas, along with a passivating gas (such as nitrogen), which is used to suppress sputtering damage of the underlying conductive regions. However, similar to the above prior art, a method for the formation and wet etch removal of a SiON film and thin pad oxide combination that have been optimized as an ARC, for the photolithographic definition of polysilicon gates, is not addressed.